Please note that the hardware not been extensively tested, but see 4 below for the cleaned up, corrected routines!.I love learning how logic designers of the past solved tricky problems with innovative solutions. The timing analyser suggests that the purely combinatiorial multiplier should be able to run at 50 MHz and the adder at 30 MHz or so. The multiplier takes about 60 logic elements plus one hardware multiplier on the CycloneII FPGA, while the adder takes about 220 logic elements. The sign is the sign of the bigger input. Shift the mantissa left until the high bit is set, while decrementing the exponent. If the signs of the inputs are different, subtract the bigger and (shifted) smaller mantissas so that the result is always positive.If the result is greater than one, shift the mantissa sum right one bit and increment the exponent. If the signs of the inputs are the same, add the bigger and (shifted) smaller mantissas.But if the exponent difference is greater than 8 then just output the bigger input. Determine the difference in the exponents and shift the smaller input mantissa right by the difference.Determine which input is bigger, which smaller (absolute value) by first comparing the exponents, then the mantissas if necessary.If both inputs are zero, the sum is zero.The sign of the product is (sign1)xor(sign2).Otherwise the second bit of the product will be set, and the output mantissa is the top 9-bits of (product)Then if (mantissa1)x(mantissa2) has the high order-bit set, the top 9-bits of the product are the output mantissa and the output exponent is exp1+exp2-128.If both inputs are nonzero and the exponents don't underflow:.If the sums of the input exponents is less than 129 then the exponent will underflow and the product is zero. The output exponent is exp1+exp2-128 or exp1+exp2-129.If either input number has a high-order bit of zero, then that input is zero and the product is zero.There are no NANs, infinities, denorms, or other special cases (which make little sense in a realtime system anyway). No error detection is performed and there is no rounding. ĭenormalized numbers are not permitted, so the high-order bit (binary value 0.5) is always one, unless the value of the FP number underflows, then it is zero. The mantissa is represented as a 9-bit fraction with a range of. The exponent is represented in 8-bit offset binary form. The 9-bit mantissa means that only one hardware multiplier (out of 70) is used for the floating multiplier. The sum of the bit-lengths (plus one sign bit) means that the FP number fits into a 18-bit M4K block word on the CycloneII FPGA. ![]() I decided to build a FP with 8-bit exponent and 9-bit mantissa (and with no NANs, infinities, denorms or rounding). Simplified, 8-bit exponent and 9-bit mantissa, Floating point. ![]() If the exponent is zero then the value should be treated as zero independent of the mantissa. ![]() The obsolete Altera documents fp_mult and fp_add_sub (see references) were useful.Ī student (Skyler Schneider, 2010) built a similar system with 18 bits of mantissa.Ī student ( Mark Eiding, 2015) modified the 18 bit system for faster inverse square root (for gravity calculations): ![]() This page shows a possible implementation. Some papers (Fang, et.al., Tong, et.al., Ehliar, et.al.) suggest that only 9 to 11 bits of mantissa is enough for video or audio encoding, as long as there is sufficient dynamic range supplied by the exponent. For parallel DSP it would be nice to have a simpler, narrow word FP. Floating Point hardware Simplified Floating Point for DSPįull IEEE 754 floating point (FP) uses a lot of hardware resource on the FPGA.
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